How a Chip Gets Printed

Start

Your phone has a brain called a chip. The biggest AI chips hold over 300 billion tiny switches. Nobody builds them by hand. They are printed, with light.

Sand to wafer

It starts as sand. Sand is full of silicon. Silicon is purified, grown into a big crystal, and sliced into shiny discs called wafers. A wafer is as wide as a school ruler is long, and thinner than a millimeter. Cut up, one wafer gives more than 600 small chips, or only about 60 giant ones.

The fab

Chips are made in a factory called a fab. Inside is a cleanroom. The air is filtered again and again. People wear bunny suits to protect the chips from skin flakes and hair. Where the pattern is printed, the lights are yellow. Blue and ultraviolet light would print by accident. One speck of dust can ruin a chip.

The print loop

Every layer goes around the same loop. Lay down a thin film. Coat it with a light-sensitive goo called photoresist. Shine a pattern of light. Wash. Carve. Add a pinch of other atoms. Clean. Then do it again. The light step can happen up to 100 times for one chip. The whole trip takes months. It is a city built one floor at a time.

Your turn: stencil

The mask is a stencil. Light gets through only where it is open. Positive resist: where light hits, it washes away. Negative resist: where light hits, it stays. Draw a pattern. Expose it. Develop it.

The brush

To paint tiny lines, you need a tiny brush. Here, the brush is light. Older machines use deep-ultraviolet light, 193 nanometers long. In one shot they print lines about 38 nanometers wide. EUV light is only 13.5 nanometers long. It prints lines about 13 nanometers wide. The newest machines, called High-NA, print lines about 8 nanometers wide. A hair is thousands of times wider than that.

For grown-ups: Resolution follows the Rayleigh equation, CD = k₁ × wavelength ÷ NA. Using ASML's quoted figures the implied k₁ is 0.27 (DUV, NA 1.35, 38 nm), 0.32 (EUV, NA 0.33, 13 nm) and 0.33 (High-NA, NA 0.55, 8 nm). k₁ depends on the process, so one constant can't reproduce all three. DUV can print finer lines with multiple exposures at higher cost; 38 nm is for one exposure. Node names like "3 nm" are marketing labels, not measured line widths.

Making the light

There is no lamp for this light. The machine makes its own. It shoots tiny drops of melted tin, about 250 kilometers an hour. A laser hits each drop twice. First to flatten it. Then to blast it into glowing plasma. The plasma is hotter than the surface of the Sun. This happens up to 50,000 times every second. We slowed it way down so you can see it.

For grown-ups: Temperature: ASML says the plasma is about 500,000 K; ZEISS says about 220,000 °C. The sources differ, so we only say it is hotter than the Sun's surface. Droplet rate: ASML says up to 50,000 per second; ZEISS says 60,000.

Mirrors

EUV light is soaked up by air and glass. So the whole machine is a vacuum, and mirrors steer the light. Each mirror stacks up to 100 thin layers and reflects up to 70 percent of the light. After four bounces, less than a quarter of the light is left. Picture one of these mirrors as big as Germany. Its tallest bump would be a tenth of a millimeter.

For grown-ups: Up to 70% per mirror is the best case. The light-left readout multiplies 0.7 per bounce to show the trend, not a measured total for ASML's tools.

Your turn: stitch

High-NA machines catch light from a wider angle. That is how they print finer lines. But the area they print at once is only half as big. So they make twice as many exposures per wafer. A giant AI chip is too big for one exposure. It is printed in two halves and joined at a seam. Slide the halves. Miss the seam, and the wire breaks.

For grown-ups: ASML says High-NA fields are half the size, so it takes twice as many exposures, and a die larger than the field must be stitched. In September 2026 ASML and TSMC announced a plan to move from 6-inch to 12-inch masks (pilot line 2031, production by 2033) to "remove stitching constraints". Intel patterns some 18A layers on High-NA (ASML, 2026-07-15). The seam rule here (the wire connects only if the halves land within half a wire's width) is a toy rule we made up; we found no published figure to model it on. A High-NA tool costs roughly US$380–400 million (press estimates, 2024–2026).

Your turn: carve

Etching carves the pattern into the layer below. A liquid eats in every direction, even sideways. It undercuts the stencil. Plasma etching shoots charged atoms straight down. The walls stay straight. Then tiny doses of other atoms are pushed into the silicon. That is called doping. It changes how the silicon carries electricity. Strip the stencil, clean the wafer, and start the next layer.

Why AI cares

An AI chip needs a huge number of switches doing math at once. High-NA lets designers fit about 2.9 times as many switches in the same space, ASML says. Only one company, ASML in the Netherlands, sells EUV machines. TSMC in Taiwan builds more made-to-order chips than anyone else. Samsung and Intel build advanced chips too. Many chip companies only design. NVIDIA designs a chip, then sends the plan to TSMC to build.

For grown-ups: Share of the foundry market, 2Q26: TrendForce reports TSMC 72.5% and Samsung 5.9% of the top-10 foundries' revenue; Counterpoint, using a different method (its market total is $96.6B vs TrendForce's $53.5B), reports TSMC 42%. Both put TSMC first. Figures are as of 2Q26.

Recap

Sand, wafer, coat, expose, develop, etch, dope. Repeat. Light is the brush. The mask is the stencil. A chip is a city printed one floor at a time.